About Me
I am a VLSI design and verification engineer with expertise in RTL coding, functional verification, and FPGA implementation. My core skills include Verilog, SystemVerilog, and digital design concepts, along with practical experience using industry standard tools such as Xilinx Vivado and ModelSim.
I have worked on projects like the design of a 1x3 router and verification of an APB to SRAM interface, which helped me gain hands on knowledge of protocols, testbench development, assertions, and waveform analysis.
I am passionate about creating efficient digital systems, delivering synthesis ready code, and ensuring reliable verification results for both academic and professional projects.
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