I am a MTech holder in electronics and communication with 5+ years of experience. I have worked both at corporate offices as well as at research organizations. I am proficient at Matlab, Fortran, Simulink, SysGen, VHDL, Verilog and Simulink. I am familiar with C and HTML. I have more than 10 international research publications including 2 SpringerBriefs and a guide for Physics ISC Class XI. I can work on various niches like programming, academic/technical/non-technical writing, blog/web content write-ups, data entry, copy-writing, etc. I am good at English and proficient at using computers. My skills at MS word, MS power-point and MS excel enable me to offer high-quality work. In addition, please note that the content provided would be 100% original, absolutely free from plagiarism....

I'm a doctorate in Engineering with subject knowledge on all core subjects I have a more than 20 years of experience on Matlab , VHDL , Verilog , spice R Python Expertise on Image processing , System Dynamics, Fluid Dynamics, Heat & Mass Transfer application FPGA, SOC, ASIC, Designs etc.......

My name is Madhushree Muralidhara, Electronic and Communication engineer graduated from East west college of Engineering....

Being an experienced electronic and electrical engineer, I offer my services to help with electrical circuit design,electrical engineering assignments, PCB design, PCB layout, MATLab, C++ ,FPGA/Verilog HDL, LabView, Proteus and Game development concepts....

Contact for your various PCB, FPGA, microcontroller design, programming, verification needs. Projects by start-ups will be done for negotiable charges. IoT and Solar based projects are welcome....

I am an electronics Engineer. Can i help you?...

I am an Electronic Engineer having experience in Digital System Design, Network Security, Digital Signal Processing and Embedded Systems. I am fluent in C, C++, Python and Verilog/VHDL, ....

RTL Design Engineer 3 years: * RTL Design Ownership: - Distributed System/L3 Cache - ACE/ACE-L/AXI slave ports for North Bridge - Distributed Register file - Routing blocks for North Bridge * Generation of North Bridge top-level and Multi Chip Topologies using Synopsys GenSys * Simulation and emulation debugging * Verification of North Bridge unit level direct tests coding - UVM, coverage analysis Validation and FPGA Engineer 8 years: 2008 – 2016 * ASIC - Logic Validation, functional tests definition and coding C, C++, low level drivers development C, C++, Assembly, hand on with hardware: - SD/MMC, SPI, NOR, UART, xMII, Packet Processor, Ethernet Switch, Ethernet MAC full responsibility - DRAM, PCIe, USB, Power Management partial responsibility * FPGA Development * RTL design - Verilog coding, implementing various bridges, communication modules, protocol exercisers, lab and debug tools * ASIC prototyping * Static Timing Analysis * Board Design...

I am working as an assistant professor at Marwadi University. I can work on electronics project like designing of analog circuits. Implementation of digital design from scratch....

I have done masters in VLSI and Embedded Systems. Currently working as FPGA design Engineer in Magna International. I have total 3 years and 10 months of experience in FPGA/RTL domain. I have expertise in FPGA design, RTL design, VHDL and Verilog languages....