I'm a doctorate in Engineering with subject knowledge on all core subjects I have a more than 20 years of experience on Matlab , VHDL , Verilog , spice R Python Expertise on Image processing , System Dynamics, Fluid Dynamics, Heat & Mass Transfer application FPGA, SOC, ASIC, Designs etc.......

I currently live in Germany, working under KIT. I have good experience in MatLab, Python, C and VHDL....

I am a very experienced embedded systems hardware and FPGA design engineer. I have worked in embedded systems design for over 20 years tending to specialize in high speed hardware design and the use of FPGA devices and VHDL to implement complex digital signal processing and image processing algorithms . I have experience system design, schematic capture and PCB layout, FPGA design and verification. I also work in C/C++ python and TCL...

I am final year student of btech electronics and communications. i would like to work as a freelancer because learning from me is the first priority i have skills and wan to add more of them....

Temporary introduction...

I am a trained data entry operator. I was also a packet core engineer in which daily live network data entry will be make.I will finish my work in given time frame....

I am a Senior Electrical engineer with over 10 years of experience in the field. The focus of my work as been in FPGA design and architecture. I am very familiar with all aspects of the design flow including high level architecture, modular design, synthesis, place and route, simulation, debug, and verification. I am fluent with the two most common HDL languages - VHDL and Verilog. I have worked on many complicated design issues such as clock-crossing, DSPs, Software registers R/W Access, and meta-stability. I have also worked through synthesis / place and route issues such as LUT / BRAM utilization, routing constraints, MMCM clocking, and timing optimization Beyond the FPGA world I also have experience in both PCB schematic design and layout. I worked on several high speed I/O designs included USB 3.1 and PCIE gen3/4. Each of those designs were modular and included multiple power rails/planes as well as PLDs, FPGAs, and microprocessors....

7+ years of experience & running a company in India. I have a team and we can work on a huge/ long-term project. Expertise in, [Languages] C, C++, Python, Java, VHDL [Development tools] Visual Studio, Eclipse, Jupyter Notebook, Xilinx, Android Studio [OS] Windows, Linux, Android [Libraries] OpenCV, DLIB, SSD, TensorFlow, Tesseract, Point Cloud, Caffee, Pytorch, Keras, Anaconda, Boost, YOLO, Alexnet & many more [Current Projects] - Human Body 3D Reconstruction for Measurements, Netherlands Long-term - OCR for Patient's Document, Australia - 2D Pose Estimation for Gym Exercise, US Long-term - 3D Pose Estimation & Emotion Recognition for Physiotherapy Exercise, Canada Long-term - Yolo v3 based Supermarket Tea/ Coffee Packets Detection & Counting, Sweden - PET Bottles Classification for Garbage Recycle Machine, India - MapNet, US Onepanel Long-term - MobileNet SSD based Object Detection, Classification & Assessment on Mobile & Cloud, US Long-term...

I am an RTL Expert, who knows both VHDL, VERILOG. I predominently worked in Image Processing projects, and have good exposure in Communication protocols...

I have good knowledge on verilog & vhdl. I have experience in protocols like UART,SPI,I2C. I know memory interfaces like DDR2,DDR3 and SRAM. Basic knowledge in python & perl scripting....