About Me
Hi, I am a VLSI Engineer specializing in RTL Design and IP Validation and have 10+ years of experience. Skilled in VHDL, Verilog for synthesizable RTL Design. Worked on various serial communication protocols I2C, SPI, UART, CAN and AMBA Bus protocols APB3, AXI4, AXI S. Skilled in TCL, PERL for scripting. EmulationRTL of Ethernet IP. Working with Microcontroller as sub system, usage of API driver files and developed few system level applications using Embedded C.Capable of investigating and trouble shooting the real time problems and guiding the team for successful completion of project in time.
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