i am an FPGA / ASIC design expert having experience of over 6 years.
I have worked on many FPGA/ASIC based projects with following skill set.
Skills : Micro architecture design, RTL design, timing closure for targeted FPGA.
Languages : Verilog , System verilog, VHDL, C/C++
Design tools : Xiline ISE, Vivado, Intel/Altera Quartus, Cadence tools for design verif and power estimation.
Protocols : Ethernet[removed]MAC, TCP/UDP implementation on FPGA, Video streaming, LPDDR, AXI, XGMAC, XGMII, 10G BASE-R PCS/PMA, SPI, I2C, I3C, and many more.
Boards/FPGAs : Virtex-7, Zedboard, Spartan-6, Spartan-3, Z-turn, Altera de nano, DE115, Red Pitaya etc
I have also worked on high end Oscilloscopes, and LabVIEW and Matlab softwares
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