About Me
During my college years, I gained valuable experience in Verilog, System Verilog and UVM, along with a strong understanding of digital and analog systems in VLSI Very Large Scale Integration. I completed numerous projects in Verilog during this period, which provided me with practical insights into developing digital systems. In addition to my coursework, I have also undergone into the world of digital design and verification, implementing assertions to ensure the correctness of these systems. This combination of theoretical knowledge and hands on project work has equipped me with a solid foundation in designing and testing complex digital and analog systems.
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