

Andhra Pradesh, India
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About Me
I don’t approach verification as a checklist—I approach it as breaking the design until the real bugs surface.
With hands on experience in SystemVerilog and transaction based environments, I focus on corner cases, protocol integrity, and failure driven testing.
I question assumptions, dig into root causes, and don’t stop at “it works”—I validate why it works.
If youre looking for a DV engineer who thinks critically and pushes designs to their limits, I’m ready to deliver.
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