Hoàng Tùng Lê
Ho Chi Minh City, Vietnam
Design Verification Engineer | SystemVerilog & UVM Mentor
Local Time - 08:49 PM
About Me
I am a Design Verification Engineer based in Vietnam with hands on experience in Digital Design and SystemVerilog/UVM Methodology.
My expertise includes:
Building full UVM Testbenches Driver, Monitor, Scoreboard, RAL.
Verifying complex protocols like AXI Stream and APB.
RTL Design Verilog for Logic blocks FSM, FIFO, RAM.
I am passionate about mentoring students and fresh engineers to master ASIC Verification concepts efficiently. I can provide clear explanations and practical coding sessions.
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$15/hr
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