
About Me
RTL Design Engineer with hands on experience designing and verifying synthesizable Verilog RTL for RISC V–based processor
cores and AMBA bus infrastructure. Proven track record delivering lint clean, simulation verified modules from microarchitecture
specification through functional sign off. Experienced in AHB Lite/APB protocol design, Clock Domain Crossing CDC, and
structured Python based verification using cocotb and pyuvm. IEEE published researcher; B.Tech ECE, CGPA 8.24.
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