Praveen Oruganti

I am a VLSI SoC Engineer with hands on industry experience in 14nm and 32nm technology nodes, delivering end to end RTL to GDSII solutions for complex digital designs. I have worked on production scale blocks including CNN accelerators, ORCA processors, and RISC V processor implementations, achieving timing closure and physical signoff within tight schedules.

My expertise includes floorplanning, power planning, placement, CTS, routing, RC extraction, and STA, using Synopsys ICC2, Design Compiler, PrimeTime, VCS, and Spyglass. I have consistently resolved a high percentage of DRC/LVS and timing violations, with strong focus on low power and high performance optimization.

In addition to physical design, I have solid experience in Verilog RTL development and RISC V Assembly ASM, including instruction level debugging, memory addressing, loop optimization, and control flow analysis. I regularly work with RISC V ISA concepts for processor validation and algorithm test