Muralikumar Jha

Muralikumar Jha

Mumbai India 1 month ago
RTL/FPGA Design and Verification engineer
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Full-time : 30+ hrs/week
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I am Muralikumar jha, i have done PG-in VLSI RTL/FPGA Design and Verification engineer. i Have 1+ Year of Experience .
i have Excellent skill of Verilog ,SV,UVM,C/C++,PERL/SHELL,Digital design,FPGA,STA, AMBA AHB/APB ,I2C.
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