, India
Verilog, systemverilog,uvm
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About Me
Bachelor's in Engineering in Electronics and communication engineer with 1 year of Professional experience, seeking an entry level position in Digital RTL Verification. Hands on experience on verification of APB, SPI, Switch, basics of Ethernet with functional coverage and System Verilog
Assertions based Verification. Strong knowledge of UVM verification methodology, Excellent knowledge in System Verilog, Digital design, CMOS fundamentals. Have worked on Industry Standard tools Synopsys VCS, Aldec Riviera Pro
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