David Levy

Estepona, Spain

5 years ago

Senior ASIC and FPGA Architect, VHDL and Verilog Designer

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Local Time - 05:54 AM

Current Availability

Part-time : 10-30 hrs/week

About Me

Senior ASIC Architect, System Engineer, HW/SW Partitioning, Senior ASIC Designer, DSP algorithms implementation. Extensive knowledge in wired and wireless communication lower layers in Telecommunication and Automotive domains.

PhD in Applied Computer Science at Slovak University of Technology STU in Bratislava, Slovakia. Thesis title: “WLAN Power Saving by Header Compression and Packet Overhearing Reduction”.

Author of 10 patents and 7 scientific papers.

I worked in Texas Instruments, Infineon and Alcatel, additionally to a few start up companies in computer communication.

My Expertise

Python

C Programming

Matlab

Field Programmable Gate Array FPGA

Verilog VHDL

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