Aiyush Aggarwal

I am a Senior R&D Engineer with over 4.5 years of industry experience in SoC level design and verification, specializing in RTL development using Verilog/SystemVerilog and delivering high quality, production ready designs.

My core expertise lies in digital design, hierarchical RTL architectures, block level and SoC integration, and developing robust testbenches and simulations using industry standard tools such as Vivado. I have hands on experience working across the full design lifecycle—from specification and RTL coding to simulation, debugging, and verification support.

In addition to hardware design, I bring strong automation and scripting capabilities, enabling efficient and scalable workflows. I am proficient in:

Python, Perl, Bash, and Tcl for design automation, regression setups, and tool flow optimization

MERN stack MongoDB, Express, React, Node.js for building internal tools, dashboards, and web based automation interfaces

This combination of SoC design expertise and s