

Hyderabad, India
Aspiring VLSI Design and Verification Engineer | RTL Design | Verilog
Local Time - 01:45 AM
About Me
I am a motivated B. Tech 3rd year Electronics and Communication Engineering student at KL University with a strong interest in VLSI design, RTL development, FPGA systems, and embedded technologies. I have knowledge of Verilog HDL, digital electronics, and simulation concepts, along with hands on experience in academic and project based implementations. I am passionate about learning new technologies and working on practical engineering solutions related to hardware design and verification.
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