About Me
VLSI engineer with over 4 years of experience, including 3+ years in RTL design and development. Experienced in LPDDR5X PHY design, mixed signal IPs, and well versed in JEDEC LPDDR5X and DFI 5.1 specifications. Known for a strategic and solution oriented mindset, adept at managing priorities under tight deadlines and contributing across the design and development cycle.
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