About Me
I am a Freelance VLSI & Embedded Systems Engineer with hands on experience in RTL Design, Functional Verification UVM, and IoT development. I specialize in Verilog, SystemVerilog, and VHDL based digital design, with proven expertise in protocols like APB, AHB, AXI, SPI, and UART.
My portfolio includes APB protocol verification using UVM, pipelined processor implementation, SPI master slave interfacing, and IoT based sensor nodes using ESP32 and STM32. I also write clean, reusable testbenches and behavioral models in SystemVerilog.
Available for remote projects in VLSI RTL design, verification, and embedded IoT prototyping.
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