About Me
I’m an experienced FPGA Design Lead with over 9+ years in the electronic design industry, specializing in communication protocols Ethernet, UART, SPI, I2C, RTL development, and high speed FPGA architectures.
Ive led teams developing 10G/40G/100G Ethernet cores, worked with Intel and Xilinx tools Quartus, Vivado, ModelSim, and delivered IPs across AXI4/Avalon protocols.
I bring deep expertise in:
RTL coding in Verilog/SystemVerilog
SoC integration, DDR simulations, and performance optimization
Partitioning large designs across multiple FPGAs AWS EC2 F1 instances
Leading & mentoring teams in agile FPGA development environments
Whether youre looking for FPGA design, protocol integration, or RTL optimization, I can help you build efficient, scalable, and reliable hardware solutions.
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