2+ Years of experience in Physical design.Well-versed with PD flow Worked in 10nm, 14nm, 16nm, 28nm technology nodes.Knowledge of physical design implementation and static timing analysis Familiar with ASIC Design Flow (Netlist to GDS II).Hands-on experience in floor planning, placement, CTS, Routing and timing closure.Experience in Synopsys ICC2, Prime Time tools.Knowledge of Signal Integrity reduction technique.Worked on the timing analysis and ECOs using the prime time

Physica Design Engineer

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