About Me
I am a verification engineer specializing in RISC V processor architectures.
I have hands on experience verifying high performance, out of order compute chiplets.
I work extensively on code and functional coverage for Load Store Units LSU.
I enjoy finding coverage gaps and closing them through targeted tests and debugging.
I am skilled in writing coverpoints for micro architectural structures.
I use tools like Questasim for UCDB analysis and regression management.
I collaborate closely with design teams to debug and resolve RTL/DV issues.
I build automation scripts to simplify coverage analysis and waiver tracking.
I am detail oriented and focused on improving verification quality and metrics.
I am passionate about building reliable and high performance processor designs.
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