Reliable and efficient code for simulation and synthesis, mainly for Xilinx and Altera FPGAs.
Careful and secure clock domain crossings.
MATLAB -- Clean and fast functions, following standard conventions.Setting up cross compilers and boot images from scratch using Buildroot, with custom kernel Product development architect.Analog layout .
Expertise in designing of IPs for speed, area and power optimizations.
Experience in FPGA prototyping of multi-million gate ASICs using Xilinx-Virtex-7, ,Zynq, Spartan6, Spartan3,Altera boards.
Understanding of Power Management voltage domain, power domains, clock domains .
Understanding of AXI protocols,Low speed protocols,Automotive Protocols
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