About Me
Senior ASIC verification Engineer with 7 years of experience working in Complex SOC-es /FPGA based projects towards complete verification life cycle test plan, test bench till coverage closure till the tapeout stage using methodologies such as SV-UVM /SV-OVM .Expertise in developing /Debugging test cases, Testbench Components and proactive in finding the bugs timely manner in both block level as well as system level for modules like I2C,DCAN,Flash controller ,SDRAM etc.
I have taken a break after that due to medical emergencies. Now I am all set to be back in the field and looking out for a challenging job.
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