

Hyderabad, India
Analog and mixed signal layout design engineer
Local Time - 08:07 AM
About Me
Analog & Mixed Signal Layout Engineer with 3+ years of experience in advanced nodes including Intel 18A/14A/7nm/5nm, TSMC
2nm, and Samsung SF2. Specialized in high performance layouts for VCO buffers, DVCs, current mirrors, LDOs, bandgaps, charge
pumps, and >16 GHz clocking networks. Expert in Cadence Virtuoso, Synopsys Custom Compiler, Calibre DRC/LVS/EMIR, and
DTCO based layout optimization. Proven track record delivering 100% DRC/LVS clean tape outs, supporting PDK bring up, and
Recipient of the Synopsys Youngest Minds Award 2025 for technical excellence and innovation.
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