About Me
I am Sai Githesh G, did PG in MIT Manipal, working as a SOC design intern in Intel.
Worked in standard cell design and physical design, nodes:45nm,180nm.
Fundamental of CMOS and RC circuits, standard cells, digital logic and circuit design, synthesis to GDSii flow.
Fundamental of STA ,Basics of scripting language.
EDA tools : cadence: genus, Innovus.
Schematic Editor: virtuoso layout Editor, Assura DRC, LVS ,QRC
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