About Me
• 12+ years of experience in Physical Design. 8 successful production chip tapeout experience.
• Experienced in leading the team to deliver quality design on scheduled timelines.
• Expertise in complete backend flow Place and Route, SI analysis, STA, PV, IR drop analysis, signoff timing closure across TSMC[removed]nm technologies.
• Excellent knowledge of EDA Tools: Cadence Encounter, Innovus, Synopsys ICC2, ICC, PT, STARRC, Mentor Caliber.
• Holds strong experience in block level Backend implementation for multi million Complex blocks. Most of the blocks with rectilinear shapes and large macro count.
• Having experience in flow setup. Ability to automate requirements using TCL scripting.
• Having experience in interacting with RTL design team to converge the designs to timing closer.
• Having experience in handling large Metal only ECOs.
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