Praveen Kumar

am a Physical Design Engineer with hands on experience in RTL to GDSII flow, particularly at advanced technology nodes like 10nm, 16nm, and 28nm. I have contributed to critical stages such as floorplanning, placement, clock tree synthesis CTS, and timing closure, using industry standard EDA tools like Fusion Compiler, Innovus, ICC II, and Primetime. My recent work at Yoctazant Technologies involved handling complex designs with over a million instances and multiple macros, where I performed timing optimization, congestion management, and ECO based fixes.

Previously, at Prime VLSI, I tackled timing critical blocks at 16nm, implementing strategies like path grouping and partial blockages to address congestion and timing violations. I have a strong command of TCL scripting, which I use extensively for automation and analysis, and I’m also proficient in Python, Verilog, and C++. With an academic background including an M.Tech in Microelectronics & VLSI from NIT Patna, I bring both theo