Nameer Ansari

NAMEER IQBAL ANSAR is a BE Computer System Engineer. Currently, contributing to the field of Semiconductor industry. With a strong focus on RISC V technology, NAMEER has dedicated 2 years to working in this field. His expertise lies in designing and testing RTL Register Transfer Level using hardware descriptive languages such as Verilog and SystemVerilog. He is proficient in tools like Xilinx, AWS FPGA, Verilator, VCS, and more, ensuring high quality results.

* The journey begins with the creation of an RV32I processor from scratch in SystemVerilog. This involved designing and implementing the processors architecture, instruction set, and control logic.

* I embarked on a project called NOVA, an Open Source System on Chip SoC that incorporated various peripherals such as UART, MATMUL, BRAM, PLIC, and CLINT, with DDR serving as the main memory. To validate the functionality and performance of the NOVA SoC, it was emulated on an AWS EC2 instance utilizing AWS Cloud FPGA capabilities.

* In my Final Year Project FYP, I worked on OpenPiton+Ariane. It is a research project aimed at developing a scalable and customizable open source processor design and cache coherence. It provides a framework for creating multicore processors with a focus on high performance and energy efficiency.

Additionally, he is a contributor to GSoC22 Google Summer of Codeprogram, and a Co Mentor for GSoC23, demonstrating his commitment to personal growth and contribution to the open source community.