About Me
I am a Goal-Oriented Senior Digital ASIC/FPGA Engineer with over ten years of experience. Several work experience enable me to pick up and own new concepts to contribute with innovative work on time is my key goal.
Verilog/FPGA/ASIC -- Reliable and efficient code for simulation and synthesis, mainly for Xilinx and Altera FPGAs. Also with experience in writing Verilog for ASIC. High awareness of device targetting in source code. Careful and secure clock domain crossings.
Perl/tcl/Make -- familiarity with the language,can write simple script to enhance the work efficiency
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