About Me
Professional Experience:
Seven+ years of experience in Analog and Mixed signal Layout Design.
Currently working on 5nm SerDes.
Worked in DSP, Automotive and RF SerDes 112Ghz projects.
I have experience in Floor-planning, Placement, Row based placement, Power Routing, schematic Driven Layout, DRC, LVS, ERC and parasitic Extraction. I have worked in IP, Padcage and full chip integration.
Have working knowledge on fin-fets layouts and it's EM-IR solving capabilities.
Have experience in 5nmTSMC, 7nmTSMC AND GF, 14nm UMC, 28nm, 40nm, 55nm and 180nm.
projects foundries : TSMC, UMC, GF
Worked in 180nm ASIL-D functional safety automotive project.
Paper work:
1. Joint layout paper on critical checks on analog layouts presented in layout conference boston.
2. Developed methodology and automation on analog layout dummy filling.
IP's in which I worked are
DDR pads,
Clock distribution,
Bandgap reference,
Low Dropout Voltage Regulator LDO,
Voltage monitors,
Temperature sensor,
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