PRO
Bengaluru, India
RTL Design & Verification Engineer | FPGA/ASIC Specialist 6+ yrs
Local Time - 04:27 AM
About Me
I am an RTL Design and Verification Engineer with 6+ years of experience in digital design, specializing in DSP algorithms, digital filters, and communication protocol IPs SPI, I2C, UART. I have contributed to multiple successful ASIC tapeouts and FPGA prototypes, handling RTL development, functional verification, MBIST testbench creation, and timing constraint development. My expertise spans Verilog, SystemVerilog, VHDL, and mixed signal simulations, with strong hands on experience in FPGA validation and integration with analog teams. I deliver efficient, high quality RTL solutions that meet performance, area, and power goals. Whether it’s IP development, verification, or FPGA testing, I help clients accelerate their design cycle with reliable results.
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