
About Me
I am a Design Verification Engineer with 4+ years of experience in SystemVerilog and UVM based verification. I specialize in verifying complex IPs and SoCs, including Memory Controllers, DMA GPDMA, Ethernet modules, Watchdog Timers, and RISC V systems.
I have strong expertise in building scalable UVM testbenches, constrained random verification, functional coverage, and assertion based verification SVA. I am experienced in debugging complex issues at both IP and SoC levels.
I have hands on experience with protocols such as AXI, AHB, APB, I2C, and SPI, including transaction level modeling, scoreboards, and coverage closure.
My key strengths include UVM testbench development, assertions, coverage modeling, debugging using waveforms, and regression management.
I am focused on delivering high quality verification solutions and ensuring design reliability. I am open to freelance opportunities in RTL verification, UVM testbench development, and debugging support.
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