Pune, Maharashtra, India
FPGA design and verification engineer
Local Time - 03:24 PM
About Me
I am currently working in VLSI field. I was awarded my M.Tech at College of Engineering, Pune and B.E at Vishwakarma Institute of Technology, Pune.
I am having 1 year 4 months of overall experience on Xilinx FPGA designing and verification using Verilog HDL. I have sound knowledge of Perl, UNIX scripting and currently i am gaining my command over System Verilog and UVM.
I always enjoy learning and researching new things. I am sincere, committed and persistent towards my work.
Explore & Appreciate my Work
Chaitannya Supe has not added any portfolio
My Project History & Feedbacks
My Endorsements
Chaitannya Supe hasn't been endorsed yet
My Education
Work Experience
Certifications
$1/hr
Total Earnings
$ 0
Projects Completed
0
Services Delivered
0
Buyer worked with
0
Feedbacks
0
Followers
Total Refund
0
Contest Completed
0
Member since
My Articles
No Articles Posted
Top Freelancers by city
Copyright © 2025 | Truelancer.com