

Hyderabad, India
VLSI Engineer | PMIC & Analog Design | RTL to GDSII | FPGA Implementat
Local Time - 07:43 AM
About Me
M.Tech VLSI Scholar & Silicon Design Engineer
Specialized in PMIC/Analog Design and the complete RTL to GDSII flow. Proven track record of ASIC Tapeout SCL 180nm and AI driven EDA research.
Technical Expertise:
PMIC & Analog: Designed Ultra Low Dropout LDO Regulators Capacitor less, Cryogenic BGRs, and Op Amps using Cadence Virtuoso, Spectre, and ADE L/XL.
Layout & Reliability: Executed full custom layouts with advanced matching Interdigitated, Common Centroid and rigorous PVT/Monte Carlo analysis.
RTL to GDSII: Owned backend flow Floorplan to Routing for Image Dehazing ASIC. Achieved timing closure and 100% DRC/LVS clean using Cadence Innovus & Siemens Calibre.
FPGA: Implemented 64 bit RISC V RV64 cores & AES 256 Accelerators on Xilinx Virtex 7, optimizing LUT/FF usage.
Automation: Developed Python/Tcl scripts to integrate AI U Net into PD flows for congestion prediction.
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