

Kotnur, India
Automation and testing engineer
Local Time - 01:43 AM
About Me
ECE graduate with industry experience in RTL design and UVM based Design/SoC Verification at Maven Silicon. Built
layered UVM testbenches achieving 95%+ functional coverage closure and sign off across multiple digital design blocks.
Proficient in constrained random verification, SystemVerilog Assertions SVA, and simulation driven debug on ModelSim
and Synopsys VCS. Experienced with APB and UART protocols; familiar with C based testbench scripting. Targeting
Qualcomms Design/SoC Verification and Digital ASIC Design tracks.
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